In a power converter using a semiconductor switching element, in the case that a semiconductor switching element, which is on, is turned off to cut off an electric current when the electric current flows from a direct current power supply in a forward direction of the semiconductor switching element (a direction from a drain to a source in the case of a MOS-FET, for example), generated is surge voltage between main terminals of the semiconductor switching element, which has been turned off, due to parasitic inductance of a power supply line. The surge voltage exceeding resistance pressure of the semiconductor switching element causes a break of the element. Accordingly, various kinds of surge voltage suppression means have been proposed up to now.
JP-A-H06-326579 (refer to Patent Reference 1) discloses an example of a conventional surge voltage suppression means. In the above means, a series circuit of a voltage regulation diode and a reverse blocking diode is connected as a gate drive circuit between a gate terminal and a drain terminal of a MOS-FET in order to limit surge voltage generated between the drain terminal and the source terminal of the MOS-FET to the predetermined voltage. When the MOS-FET is off-driven and the current flowing to a load is cut off, parasitic inductance of a power supply line causes surge voltage between the drain terminal and the source terminal of the MOS-FET. The surge voltage exceeding the sum of breakdown voltage of the voltage regulation diode and forward direction voltage of the reverse blocking diode causes an electric current to flow from a drain to a gate of the MOS-FET to turn on the MOS-FET. This allows the MOS-FET to absorb energy of parasitic inductance while the surge voltage is limited to the predetermined voltage.
In the case of applying the conventional gate drive circuit of a semiconductor switching element to a polyphase bridge type power converter, however, energy of parasitic inductance consumed in turning off a semiconductor switch in respective phases concentrates on a semiconductor switching element in a specific phase in accordance with dispersion of characteristics of the voltage regulation diode. This causes possibility of an overheat break due to an increase in loss.
Further, uneven loss of the respective semiconductor switching elements requires heat design carried out so as to correspond to a semiconductor switching element having the greatest loss. This causes a problem that a heat dissipation circuit of the power converter to be made large, which goes against the times of miniaturization and lightening of weight in a field of devices for a vehicle.
Now, a case shown in FIGS. 9 to 11 that the gate drive circuit is applied to a power converter for a vehicle will be exemplified to describe problems in the prior art in detail. FIG. 9 illustrates a whole structure of a system for converting direct current power of a battery 90 into three-phase alternating current power by means of a power converter 70 to drive a motor generator 80 so as to drive an engine and for rectifying and converting by means of the power converter 70 three-phase alternating current power, which is caused by rotation of the motor generator 80 in accordance with a drive of the engine, into direct current power. Ldc denotes parasitic inductance of wiring of a direct current power supply line between the battery 90 and the power converter 70.
A field system circuit, a sensor circuit and such are omitted from drawing. The power converter 70 is a three-phase bridge circuit comprising N-channel type power MOS-FETs 30a to 30f. The battery 90 is connected between a high voltage side direct current terminal P and a low voltage side direct current terminal N of the power converter 70. Alternating current terminals U, V and W connected to middle points of respective phases (a phase U, a phase V and a phase W) of the three-phase bridge are respectively connected to stator windings U, V and W of the motor generator 80. Power MOS-FETs 50a to 50f are connected to the gate drive circuits 30a to 30f and further to a control circuit 40 upstream from the gate drive circuits.
FIG. 10 illustrates an inner circuit of the gate drive circuit 30a in FIG. 9. A gate driver 20 drives the power MOS-FET 50a through a gate resistance Rg in accordance with an on-off control signal UH of the control circuit 40. Between a gate terminal and a drain terminal of the power MOS-FET 50a, connected is a series circuit of a voltage regulation diode Z1a and a reverse blocking diode D1. The insides of the other gate drive circuits 30b to 30f in FIG. 9 are similar to the circuitry in FIG. 10. It is assumed that Z1b to Z1f denote respective voltage regulation diodes and that breakdown voltages of voltage regulation diodes Z1c and Z1d of the gate drive circuits 30c and 30d in the phase V are smaller than those of the voltage regulation diodes Z1a, Z1b, Z1e and Z1f in the other phases by several volts.
FIG. 11 shows operation waveforms in the case that a rectangular wave controls signal having an energizing angle of 180 degrees is outputted from the control circuit 40 and alternating current power having a predetermined frequency is given to the motor generator 80 for a drive in FIG. 9. UH, UL, VH, VL, WH and WL denote on-off control signals of the respective power MOS-FETs 50a to 50f, which are outputted from the control circuit 40. A signal at a high level means an instruction of “on” while a signal at a low level means an instruction of “off”. Time for preventing short circuit (dead time) is provided in timing of switching on and off a control signal. Vpn denotes a voltage between the terminal P and the terminal N of the power converter 70. Vgs (50a), Vgs (50b), Vgs (50c), Vgs (50d), Vgs (50e) and Vgs (50f) respectively denote voltages between gates and sources of the power MOS-FETs 50a to 50f. A section of a middle voltage shows the gate drive circuits 30a to 30f operating so as to limit the surge voltage due to the parasitic inductance Ldc to a predetermined value.
Now, described will be an operation in FIG. 11. When Vgs (50c) decreases on the basis of an instruction of turning off in accordance with VH to turn off the power MOS-FET 50c, for example, surge voltage due to the parasitic inductance Ldc is generated between the drain and the source of the power MOS-FET 50c while surge voltage at the substantially same level is generated for Vpn. The surge voltage exceeding the sum of breakdown voltage of the voltage regulation diode Z1c of the gate drive circuit 30c and forward direction voltage of the reverse blocking diode D1 causes Vgs (50c) to slowly decrease in the vicinity of an on-threshold value of the power MOS-FET 50c. The surge voltage is then limited to a predetermined level of the gate drive circuit 30c while the power MOS-FET 50c absorbs energy of the parasitic inductance Ldc. That is to say, the power MOS-FET 50c, which has been turned off, absorbs the energy of the parasitic inductance Ldc.
When the MOS-FETs 50b and 50e are turned off on the basis of instructions of turning off in accordance with UL and WH to generate surge voltage to Vpn, however, the gate drive circuit 30c of the power MOS-FET 50c, which has been turned off, in the phase V where breakdown voltage of the voltage regulation diode is low responds first to the generated surge voltage. As a result, Vgs (50c) rises to the vicinity of the on-threshold of the power MOS-FET 50c to turn on the power MOS-FET 50c. The surge voltage is then limited to a predetermined level of the gate drive circuit 30c while the power MOS-FET 50c absorbs energy of the parasitic inductance Ldc. That is to say, MOS-FET 50c, which is controlled by the gate drive circuit 30c having low breakdown voltage of the voltage regulation diode, instead of the power MOS-FETs 50b and 50e, which have been turned off, absorbs energy of the parasitic inductance Ldc. Similarly, the power MOS-FET 50d absorbs energy of the parasitic inductance Ldc, which is consumed in turning off the power MOS-FETs 50a, 50d and 50f. 
As described above, it can be considered that a power MOS-FET in a specific phase, which is controlled by a gate drive circuit having low breakdown voltage of a voltage regulation diode, absorbs not only the energy of the parasitic inductance Ldc, which is consumed in turning off the power MOS-FET in the self phase, but also all energy of the parasitic inductance Ldc, which is consumed in turning off the power MOS-FET in the other phases, in accordance with a state of dispersion of the breakdown voltage of the voltage regulation diode forming the gate drive circuit. The power MOS-FET in the specific phase is likely to be led to an overheat break due to an increase in loss. Further, uneven loss of the respective semiconductor switches causes necessity of heat design corresponding to a semiconductor switch having the greatest loss. This causes a large-scaled heat dissipation circuit of a power converter.